1. Field of the Invention
This invention relates to a method of encoding digital data. In addition, this invention relates to an apparatus for encoding digital data. Furthermore, this invention relates to a recording medium.
2. Description of the Related Art
Some modulation (encoding) procedures used for digital signals recorded on recording mediums are of a RLL (d, k) type, where xe2x80x9cRLL (d, k)xe2x80x9d means run length limiting rules such that xe2x80x9cdxe2x80x9d to xe2x80x9ckxe2x80x9d successive bits of xe2x80x9c0xe2x80x9d should be between bits of xe2x80x9c1xe2x80x9d in a modulation-resultant bit stream.
Japanese patent application publication number 9-232963/1997 discloses an RLL (1, 7) modulation procedure for a digital signal. The modulation procedure in Japanese application 9-232963 includes a step of encoding a 2-bit or 4-bit input data piece into a 3-bit or 6-bit output code word by referring to conversion tables. The encoding is of the variable length type. The conversion tables are based on the following assignment of input data pieces to output code words.
where xe2x80x9cxxe2x80x9d denotes an indefinite bit which is xe2x80x9c0xe2x80x9d when the last bit of an immediately-preceding output code word is xe2x80x9c1xe2x80x9d, and which is xe2x80x9c1xe2x80x9d when the last bit of an immediately-preceding output code word is xe2x80x9c0xe2x80x9d. The above-indicated 2-bit input data pieces correspond to a constraint length of xe2x80x9c1xe2x80x9d, while the above-indicated 4-bit input data pieces correspond to a constraint length of xe2x80x9c2xe2x80x9d.
The modulation procedure in Japanese application 9-232963 implements signal processing for indefinite bits, and executes a decision as to whether a current input data piece corresponds to a constraint length of xe2x80x9c1xe2x80x9d or xe2x80x9c2xe2x80x9d. Therefore, an apparatus for carrying out the modulation procedure is complicated in structure.
Japanese patent application publication number 11-346154/1999 discloses an RLL (1, 7) modulation apparatus which includes an inserting section which adds DSV control bits to an input data sequence. The inserting section outputs the DSV-control-bit-added data to a modulator. The modulator handles the output data from the inserting section as data having a basic data length of 2 bits. According to conversion tables, the modulator converts the output data from the inserting section into data of a variable length code having a basic data length of 3 bits. The modulator outputs the variable-length-code data to an NRZI converter. The conversion tables have a replacement code for restricting succession of a minimum run to a prescribed number of times or less, and a replacement code for observing the run length limiting rules. The conversion tables further have a conversion rule such that the remainder in the division of the number of bits of xe2x80x9c1xe2x80x9d in each input element by 2 and the remainder in the division of the number of bits of xe2x80x9c1xe2x80x9d in a corresponding output element by 2 are equal to each other as 1 or 0. Thus, each input element and a corresponding output element are equal in polarity (xe2x80x9codd-evenxe2x80x9d in the number of bits of xe2x80x9c1xe2x80x9d in an element).
In Japanese application 11-346154, the modulator encodes a 2-bit, or 8-bit input data piece into a 3-bit, 6-bit, 9-bit, or 12bit output code word by referring to the conversion tables. The encoding is of the variable length type. The conversion tables are based on the following assignment of input data pieces to output code words.
The above-indicated 2-bit input data pieces correspond to a constraint length of xe2x80x9c1xe2x80x9d. The above-indicated 4-bit input data pieces correspond to a constraint length of xe2x80x9c2xe2x80x9d. The above-indicated 6-bit input data pieces correspond to a constraint length of xe2x80x9c3xe2x80x9d. The above-indicated 8-bit input data pieces correspond to a constraint length of xe2x80x9c4xe2x80x9d.
The modulation apparatus in Japanese application 11-346154 includes a portion for deciding which of constraint lengths a current input data piece corresponds to. Therefore, the modulation apparatus is complicated in structure.
It is a first object of this invention to provide a relatively simple method of encoding digital data.
It is a second object of this invention to provide a relatively simple apparatus for encoding digital data.
It is a third object of this invention to provide an improved recording medium.
A first aspect of this invention provides a method of encoding an input bit stream into a stream of output code words according to variable-length encoding rules using a variable constraint length, wherein a maximum value N of the constraint length is equal to or greater than 2, and the output-code-word stream observes prescribed run length limiting rules RLL (d, k), xe2x80x9cdxe2x80x9d and xe2x80x9ckxe2x80x9d denoting a predetermined minimum run length and a predetermined maximum run length respectively. The method comprises the steps of preparing M encoding tables in accordance with the variable-length encoding rules, M denoting a predetermined natural number equal to or greater than 2; periodically inserting a DSV control bit into a first input bit stream at intervals each corresponding to a prescribed number of successive bits in the first input bit stream to change the first input bit stream into a second input bit stream: encoding every m-bit piece of the second input bit stream into an n-bit output signal forming at least a portion of an output code word by referring to the M encoding tables, thereby converting the second input bit stream into a first output bit stream composed of output code words and observing the prescribed run length limiting rules RLL (d, k), xe2x80x9cmxe2x80x9d and xe2x80x9cnxe2x80x9d denoting predetermined natural numbers respectively; inserting a sync word of a predetermined bit pattern into the first output bit stream for every frame to change the first output bit stream into a second output bit stream; terminating a frame-end output code word at a position before a next-frame sync word; and implementing DSV control of the second output bit stream in response to the inserted DSV control bits.
A second aspect of this invention is based on the first aspect thereof, and provides a method wherein the M encoding tables register input bit patterns corresponding to the m-bit piece of the second input bit stream, n-bit output signals assigned to the input bit patterns respectively, and next-table selection numbers accompanying the n-bit output signals respectively and each designating one among the M encoding tables which will be used next; wherein the encoding step comprises encoding every m-bit piece of the second input bit stream into an n-bit output signal by referring to one of the M encoding tables which is designated by a current-table selection number being a next-table selection number provided by preceding encoding, and reading a next-table selection number accompanying the n-bit output signal from the designated one of the M encoding tables; and wherein the enabling step comprises using a termination table which registers at least one input bit pattern corresponding to the m-bit piece of the second input bit stream, at least one n-bit output signal assigned to the input bit pattern, and at least one next-table selection number accompanying the n-bit output signal and designating one among the M encoding tables which will be used next.
A third aspect of this invention is based on the first aspect thereof, and provides a method wherein the numbers xe2x80x9cdxe2x80x9d and xe2x80x9ckxe2x80x9d are equal to 1 and 7, respectively.
A fourth aspect of this invention provides an apparatus for encoding an input bit stream into a stream of output code words according to variable-length encoding rules using a variable constraint length, wherein a maximum value N of the constraint length is equal to or greater than 2, and the output-code-word stream observes prescribed run length limiting rules RLL (d, k), xe2x80x9cdxe2x80x9d and xe2x80x9ckxe2x80x9d denoting a predetermined minimum run length and a predetermined maximum run length respectively. The apparatus comprises M encoding tables accorded with the variable-length encoding rules, M denoting a predetermined natural number equal to or greater than 2, the M encoding tables registering input bit patterns corresponding to an m-bit piece of an input bit stream, n-bit output signals assigned to the input bit patterns respectively, and next-table selection numbers accompanying the n-bit output signals respectively and each designating one among the M encoding tables which will be used next; means for periodically inserting a DSV control bit into a first input bit stream at intervals each corresponding to a prescribed number of successive bits in the first input bit stream to change the first input bit stream into a second input bit stream; means for encoding every m-bit piece of the second input bit stream into an n-bit output signal forming at least a portion of an output code word by referring to one of the M encoding tables which is designated by a current-table selection number being a next-table selection number provided by preceding encoding, and reading a next-table selection number accompanying the n-bit output signal from the designated one of the M encoding tables, thereby converting the second input bit stream into a first output bit stream composed of output code words and observing the prescribed run length limiting rules RLL (d, k), xe2x80x9cmxe2x80x9d and xe2x80x9cnxe2x80x9d denoting predetermined natural numbers respectively; means for inserting a sync word of a predetermined bit pattern into the first output bit stream for every frame to change the first output bit stream into a second output bit stream; means for terminating a frame-end output code word at a position before a next-frame sync word; and means for implementing DSV control of the second output bit stream in response to the inserted DSV control bits.
A fifth aspect of this invention is based on the fourth aspect thereof, and provides an apparatus wherein the numbers xe2x80x9cdxe2x80x9d and xe2x80x9ckxe2x80x9d are equal to 1 and 7, respectively.
A sixth aspect of this invention provides a recording medium storing a second output bit stream generated from a first input bit stream by the method of the first aspect of this invention.
A seventh aspect of this invention is based on the second aspect thereof, and provides a method wherein the numbers xe2x80x9cdxe2x80x9d and xe2x80x9ckxe2x80x9d are equal to 1 and 7, respectively.
An eighth aspect of this invention provides a recording medium storing a second output bit stream generated from a first input bit stream by the method of the second aspect of this invention.